1. Field of the Invention
The present invention relates to a display control apparatus for controlling the display of a display device.
2. Related Background Art
In a recent display system of a computer, a system to read in not only characters and lines but also a natural image and combine it with the characters and lines for display has been put into practice. This means that a halftone (gray level) display function of a display device (liquid crystal, plasma or EL) in the display system has become an important part. However, the halftone display is hot easy in a display device other than a CRT, for example, a liquid crystal display device, particularly a ferroelectric liquid crystal display device.
As to a display element which uses the ferroelectric liquid crystal (FLC), it has been known to arrange two glass substrates to face each other while maintaining a cell gap of 1-3 .mu.m and form transparent electrodes on the facing planes thereof, and to orient the transparent electrodes to form a liquid crystal cell, in which ferroelectric liquid crystal is filled, as disclosed in U.S. Pat. No. 4,964,699.
Features of the display element which uses the ferroelectric liquid crystal are that the ferroelectric liquid crystal has a spontaneous polarization which can be used for switching an external electric field and a coupling force of the spontaneous polarization, and that it can be switched by a polarity of the external electric field because a longitudinal direction of a ferroelectric liquid crystal molecule corresponds to a direction of polarization of the spontaneous polarization.
The ferroelectric liquid crystal is primarily used for a binary (black and white) display element by using a light transmission state and a light block state as two stable states.
FIG. 2 shows a relation between an amplitude of a switching pulse of a ferroelectric liquid crystal element and a transmission factor. A transmitted light intensity I when a one-shot pulse of one polarity is applied to a cell (element) in a perfectly light blocking (black) state is plotted as a function of an amplitude V of the one-shot pulse. When the pulse amplitude is lower than a threshold Vth (V&lt;Vth), the transmitted light intensity does not change and the transmission status of a pixel after the application of the pulse does not change from a status of the pixel prior to the application shown in FIG. 3A, as shown in FIG. 3B. When the pulse amplitude V exceeds the threshold (Vth&lt;V&lt;Vsat), portions of pixels shift to the other stable state, that is, a light transmission status shown in FIG. 3C so that an intermediate light transmission is exhibited as a total. When the pulse amplitude V further increases and exceeds a saturation level Vsat (Vsat&lt;V), all pixels are shifted to the light transmission status and the light intensity reaches a constant level as shown in FIG. 3D.
As seen from FIGS. 2 and 3A to 3D, the pulse amplitude V should be controlled to meet the condition of Vth&lt;V&lt;Vsat in order to conduct the halftone display in the ferroelectric liquid crystal element. However, because a gradient of the light intensity between Vth and Vsat is sharp, it is difficult to accurately control the halftone by the pulse amplitude V. Since the relation between the voltage V and the transmitted light intensity I shown in FIG. 4 depends on the cell thickness and the temperature, different gradation levels may be displayed for applied pulses of the same voltage amplitude if a cell thickness distribution or a temperature distribution is included in the display panel.
While the FLC has been discussed above, the same is applied to TN liquid crystal having no active element when a number of halftone levels are to be attained.
In order to solve the above problems, it has been proposed in U.S. patent application Ser. No. 08/062,214 to digitally process image information in the two states of FIGS. 3B and 3D to attain a pseudo halftone display (or quasi-gray level display).
On the other hand, a method of "low frame frequency drive+partial writing scan" (Japanese unexamined Patent Publication (KOKAI) No. 63-65494 and Japanese Unexamined Patent Publication (KOKAI) No. 63-285141) has been proposed as a drive method for high resolution display in the ferroelectric liquid crystal display or a display device having a memory property and it is an essential drive method in the ferroelectric liquid crystal drive.
However, the following problems arise when the multi-interlace scan by the low frame frequency drive and the random line scan by the partial writing drive are applied to the binary pseudo halftone display process.
In the binary pseudo halftone display process, a method by using an error spread has been known in which an error which is created by binarizing a pixel under consideration by a threshold is sequentially spread to periphery of the cell under consideration and the peripheral pixels having the errors distributed are binarized by threshold levels having the errors added thereto. The halftone information is saved in macro to conduct the pseudo halftone level display. Accordingly, in order to attain the reproducibility of pseudo halftone display, it is necessary to distribute the error to the periphery of the pixel in which the error has been created and the process by the non-interlace scan is required. If the binarization process is conducted in accordance with the multi-interlace and random interlace scan sequence to meet the above requirements, a positional balance of saving of the halftone information is destroyed and the reproducibility of the halftone is lowered.
Further, when the pseudo halftone process is conducted to all image signals sent from a computer, a character deformation or a drop of dot occurs in the character or a fine line. This is due to the fact that the pseudo halftone process conducts the halftone display in macro.
When the pseudo halftone processing function and the partial writing function are performed by a unit externally of the display device (for example, a unit in a computer), it is necessary to modify the software and the hardware for a graphic control unit in the computer. This means a difficulty in attaining university of the display device.
In order to solve the above problem, it is preferable to directly process a CRT display signal which is common in a display device of the computer. However, in order to receive the CRT display signal and detect the partial writing, a frame memory of at least one frame capacity is required because the CRT display signal is outputted frame by frame. This causes a problem of the increase of the capacity of the frame memory in a high resolution display device having more than 1000.times.1000 pixels, and the increase of a system cost and a size.